The present invention relates generally to the field of low power digital wireless communications and, more specifically, to radio communication links that provide for low power consumption and compact size while maintaining accurate frequency synthesized tuning and effective performance.
The purpose of frequency synthesis is the generation of radio waveforms whose frequency is conveniently and accurately controlled. Frequency accuracy is important for state-of-the-art radio equipment to allow for the efficient use of the radio spectrum by exact placement of the transmit frequency. This allows channels to be tightly packed and for minimum receiver bandwidth and, thus, higher sensitivity for a given data rate. Frequency synthesis using the phase locked loop (PLL) technique is the dominant method to provide for such accuracy. The fundamental operation of PLL frequency synthesis is well known, described, and analyzed in the literature, such as R. Best, Phase Locked Loops, Theory, Design, and Applications, New York: McGraw Hill, 1984.
The PLL frequency synthesizing approach is based on a feedback control system with phase as the control variable. The phase of the desired output signal is forced to be a constant in this system. Because frequency is, by definition, the mathematical derivative of phase with respect to time, frequency error is forced to zero when phase error is held constant. In the circuit implementation of a PLL, the phase of a block consisting of a voltage controlled oscillator (VCO) followed by a frequency divider is, by use of negative feedback, kept matched to the phase of a block consisting of a crystal controlled oscillator (XCO) followed by a different divider. The two divider outputs drive a phase detector that outputs a signal proportional to the phase difference between the inputs. The phase detector output is filtered by a loop filter to remove excess noise. The filtered output steers the VCO by its control voltage to the desired frequency. Since the XCO has very accurate frequency control, that accuracy is transferred to the VCO, achieving a highly accurate frequency output, usually at much higher frequencies than the XCO can achieve alone, and having the capability to be set to a wide range of frequencies by electronically programming the dividers. This reprogramming is usually under software control.
Expanding wireless applications such as cellular telephones have spurred the recent development of phase locked loop synthesizer integrated circuits to provide all the required frequency dividers and the phase detector of a PLL synthesizer in one compact integrated circuit package, with the voltage controlled oscillator and loop filter usually implemented with discrete components or separate modules. In most implementations multiple radio frequency (RF) buffer amplifiers are also employed with the VCO, both to provide isolation of the VCO from disturbing outside influences and to provide a means of controlling the output amplitude of the generated signal. Crystal reference oscillator modules usually referred to as Temperature Compensated Crystal Oscillators (TCXO's) are commonly used. These modules are trimmed in manufacturing to be exactly on frequency, and are usually voltage controllable over a range that is small but still sufficient to steer the TCXO to stay exactly on frequency over the temperature range over which the system must operate.
While this design approach provides sufficient size, power, and cost efficiency for markets such as cellular telephones, there is a large class of short range wireless equipment whose size, power, and cost constraints are much more severe. These applications include automatic identification, keyless entry systems, status reporting, security systems, control systems, simple local area networks, and many other local area wireless data links. To date, even with the advances promoted by the success of the cellular and other wireless markets, the constraints of this very low power market have prevented the use of frequency synthesis in this class of equipment. The specific difficulties encountered in applying frequency synthesis to this very low power market include power consumption, implementation of frequency modulation inside a phase locked loop, dealing with degraded frequency accuracy resulting from the least expensive class of crystals, and general cost and size issues. The unacceptable DC power consumption is the result of power usually consumed in the synthesizer IC, the VCO and RF buffers, and the TCXO. The difficulty of implementing FM results from the fact that the phase locked loop responds to frequency modulation the same way it does to any other source of frequency error, and acts to remove such error. But in the case of deliberate frequency modulation, this correction results in distortion of the desired modulation.
Two other practical implementation difficulties also arise when attempting design of highly efficient FM wireless data systems where the FM is generated within a phase locked loop. First, the VCO tune slope, or the ratio of frequency change per volt, is nonlinear and usually varies significantly over the desired band of operation. Thus a constant modulation voltage applied to the VCO when at different carrier frequencies results in undesired variation in the system frequency deviation over the band of operation. The other problem is a tendency to move the carrier frequency off that desired by the initiation of modulation.
Because of these difficulties in applying synthesized systems to the low power market, the standard technology now applied to meet the severe constraints of the market is based upon Surface Acoustic Wave (SAW) devices. These are basically crystals with the resonant acoustic mode constrained to the surface area of the crystal, which allows the SAW crystal to go to much higher frequency than typical bulk mode crystals. The SAW device is used to stabilize the frequency of a simple oscillator circuit, allowing compact, low power, and low cost generation of the required radio frequency carrier. Amplitude modulation is conveniently applied to an RF buffer stage or directly to the SAW stabilized oscillator. However, such technology has significant performance disadvantages compared to frequency synthesis. These disadvantages include only single charmel operation, poor frequency accuracy, and difficulty in using the superior technique of frequency modulation. The difficulty in attaining acceptable frequency modulation performance almost always results in use of amplitude modulation (AM), with subsequent severe multipath fade degradation.
If frequency modulation can be directly applied to a phase locked loop, then a high degree of circuit efficiency can be attained. In seeking this desirable goal there is a long history of attempts to directly modulate PLL synthesizers in radio link and other equipment has resulted. U.S. Pat. No. 3,393,380 granted to Webb and assigned to the National Aeronautics and Space Administration, PHASE LOCKED PHASE MODULATOR INCLUDING A VOLTAGE CONTROLLED OSCILLATOR, 1968, presents an early example of frequency modulation of a phase locked loop. This simple early form injects the modulation into the phase detector output, which has the disadvantages of limited modulation rate due to the filtering action of the subsequent low pass loop filter, as well as allowing distortion to be introduced by the response of the phase locked loop to the modulation. It did, however, represent an advance on the frequency modulation techniques used at the time. The intended application was space communications. No power consumption reduction techniques are presented, nor any method of preventing the phase locked loop from distorting the desired FM.
U.S. Pat. No. 5,097,230 to Lautzenhiser and assigned to Emhiser Research Limited, PHASE LOCKED LOOP THAT INCLUDES D.C. MODULATION, is typical of a set of patents that allow the highly desirable feature of D.C. modulation in a phase locked loop. This complicated technique and other similar methods are highly applicable and usefull in classes of equipment that are not extremely size, cost, and power limited. For low power wireless such techniques cannot meet the severe constraints on those same parameters.
U.S. Pat. No. 5,493,257 to Chadwick and assigned to Plessy Semiconductor Limited, MODULATOR WITH BIASING CIRCUIT TO MINIMIZE OUTPUT DISTORTION, presents a method for efficient implementation of "mid point" modulation in an FM PLL system. Midpoint modulation may be defined as a method of initiating modulation from the carrier out to the state that defines a logic one or zero, such that initial deviation is one half of the peak to peak deviation. However, the technique presented by Chadwick is limited to A.C. coupling of the desired modulation. U.S. Pat. No. 4,609,886 to Takaki and assigned to Pioneer Electronic Corporation, PLL MODULATION CIRCUIT, presents a method of attaining true D.C. coupling in an FM PLL system, but the method is overly complex and expensive for use in low power wireless.
U.S. Pat. No. 5,379,002, to Jokura and assigned to NEC Corporation, FREQUENCY SYNTHESIZER USING INTERMITTENTLY CONTROLLED PHASE LOCKED LOOP, teaches a fast switching frequency synthesizer circuit employing an intermittently controlled PLL along with a control voltage coarse adjustment circuit. Power savings are claimed in that the lock seek time is minimized. The invention presented by this Jokura patent is specifically intended for rapid channel switching in a Time Division Multiple Access (TDMA) cellular system, and is not optimized for a mode of operation or the minimum power and component count demanded in very low power digital wireless applications.
Accordingly, a need still exists for an apparatus which provides a form of PLL synthesizer based communications equipment for use in very compact, low power, low cost, and minimum component count radio communications equipment.